In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.

Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA

Lazzari, Federico
;
Bassi, Giovanni
;
Cenci, Riccardo
;
Morello, Michael J.
;
Punzi, Giovanni
2020

Abstract

In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.
Settore FIS/01 - Fisica Sperimentale
19th International Workshop on Advanced Computing and Analysis Techniques in Physics Research 11-15 March 2019, Saas-Fee, Switzerland
Volume 1525
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11384/101588
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