We present the latest results on the prototype of a tracking processor capable of reconstructing events in a silicon-strip tracker at about 40 MHz event rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement one of the first functional prototype of this processor on a DAQ board based on Alters Stratix III FPGAs. Then, in order to test the maximum rate capability, we port and optimize the processor on a high-speed board equipped with Altera Stratix V FPGAs. Future applications of this novel approach as real-time track trigger at LHC experiments are also discussed.

Development of a high-throughput tracking processor on FPGA boards

Cenci, Riccardo
;
Punzi, Giovanni;Marino, Pietro;Morello, Michael Joseph;Ristori, Luciano F.;Stracka, Simone;
2017

Abstract

We present the latest results on the prototype of a tracking processor capable of reconstructing events in a silicon-strip tracker at about 40 MHz event rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement one of the first functional prototype of this processor on a DAQ board based on Alters Stratix III FPGAs. Then, in order to test the maximum rate capability, we port and optimize the processor on a high-speed board equipped with Altera Stratix V FPGAs. Future applications of this novel approach as real-time track trigger at LHC experiments are also discussed.
2017
Settore FIS/01 - Fisica Sperimentale
TWEPP 17 : Topical Workshop on Electronics for Particle Physics
Santa Cruz, California
11 - 14 September 2017
Topical Workshop on Electronics for Particle Physics : TWEPP 17 : 11 - 14 September 2017, Santa Cruz, California
Sissa Medialab
Pattern recognition systems; Artificial retinas; Design and implements; Functional Prototypes; Future applications; High-speed boards; Pattern recognition algorithms; Rate capabilities; Silicon strip tracker; Field programmable gate arrays (FPGA)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11384/141189
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