We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices. (C) 2015 Elsevier B.V. All rights reserved.

An "artificial retina" processor for track reconstruction at the full LHC crossing rate

CENCI, RICCARDO;MARINO, PIETRO;MORELLO, MICHAEL JOSEPH;
2016-01-01

Abstract

We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices. (C) 2015 Elsevier B.V. All rights reserved.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11384/66092
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